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Commits (2)
# Ignoring temporary schematic, board, library and lock files:
*.s#[0-9#]
*.b#[0-9#]
*.l#[0-9#]
*.s$[0-9$#]
*.b$[0-9$#]
*.l$[0-9$#]
*.lck
# Ignore emacs buffered files
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......@@ -239,6 +239,20 @@ Enfolib is a collection of various self-created components. Some are modificatio
<text x="-5.08" y="4.445" size="1.27" layer="21">&gt;NAME</text>
<text x="-5.08" y="-10.795" size="1.27" layer="21">&gt;VALUE</text>
</package>
<package name="JST-GH-SIDE-4">
<smd name="1" x="-1.9" y="2.01" dx="0.6" dy="1.7" layer="1"/>
<smd name="2" x="-0.65" y="2.01" dx="0.6" dy="1.7" layer="1"/>
<smd name="6" x="-4.05" y="-1.19" dx="1" dy="2.7" layer="1"/>
<smd name="7" x="4.04" y="-1.19" dx="1" dy="2.7" layer="1"/>
<wire x1="-4.4" y1="2.15" x2="4.39" y2="2.15" width="0.127" layer="21"/>
<wire x1="4.39" y1="2.15" x2="4.39" y2="-2.35" width="0.127" layer="21"/>
<wire x1="4.39" y1="-2.35" x2="-4.4" y2="-2.35" width="0.127" layer="21"/>
<wire x1="-4.4" y1="-2.35" x2="-4.4" y2="2.15" width="0.127" layer="21"/>
<smd name="3" x="0.62" y="2.01" dx="0.6" dy="1.7" layer="1"/>
<smd name="4" x="1.89" y="2.01" dx="0.6" dy="1.7" layer="1"/>
<text x="0" y="3.75" size="1.27" layer="25" ratio="20" align="bottom-center">&gt;NAME</text>
<text x="-3.81" y="-5.08" size="1.27" layer="27">&gt;VALUE</text>
</package>
</packages>
<symbols>
<symbol name="ADIS_CONN">
......@@ -291,6 +305,24 @@ Enfolib is a collection of various self-created components. Some are modificatio
<pin name="9" x="-7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1"/>
<pin name="10" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
</symbol>
<symbol name="CONN_04">
<description>&lt;h3&gt;4 Pin Connection&lt;/h3&gt;</description>
<wire x1="3.81" y1="-7.62" x2="-5.08" y2="-7.62" width="0.4064" layer="94"/>
<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
<wire x1="-5.08" y1="7.62" x2="-5.08" y2="-7.62" width="0.4064" layer="94"/>
<wire x1="3.81" y1="-7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
<wire x1="-5.08" y1="7.62" x2="3.81" y2="7.62" width="0.4064" layer="94"/>
<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
<text x="-5.08" y="-9.906" size="1.778" layer="96" font="vector">&gt;VALUE</text>
<text x="-5.08" y="8.128" size="1.778" layer="95" font="vector">&gt;NAME</text>
<pin name="1" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
<pin name="2" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
<pin name="3" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
<pin name="4" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
<pin name="MNT" x="-7.62" y="-5.08" length="short"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="ADIS_HD">
......@@ -343,6 +375,25 @@ Enfolib is a collection of various self-created components. Some are modificatio
</device>
</devices>
</deviceset>
<deviceset name="CONN-4">
<gates>
<gate name="B" symbol="CONN_04" x="0" y="0"/>
</gates>
<devices>
<device name="" package="JST-GH-SIDE-4">
<connects>
<connect gate="B" pin="1" pad="1"/>
<connect gate="B" pin="2" pad="2"/>
<connect gate="B" pin="3" pad="3"/>
<connect gate="B" pin="4" pad="4"/>
<connect gate="B" pin="MNT" pad="6 7"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="resistor" urn="urn:adsk.eagle:library:348">
......@@ -7233,14 +7284,15 @@ Source: http://www.murata.com .. GRM43DR72E224KW01.pdf</description>
<part name="C3" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="C-US" device="C0603" package3d_urn="urn:adsk.eagle:package:26138/1"/>
<part name="FRAME1" library="frames" library_urn="urn:adsk.eagle:library:229" deviceset="DOCFIELD" device=""/>
<part name="JST-SM10B-GHDS" library="enfolib" deviceset="HEADER10" device="" value="JST-SM10B-GHDS"/>
<part name="R2" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-US_" device="R0603" package3d_urn="urn:adsk.eagle:package:26057/1" value="0R"/>
<part name="J1" library="resistor" library_urn="urn:adsk.eagle:library:348" deviceset="R-US_" device="R0603" package3d_urn="urn:adsk.eagle:package:26057/1" value="0R"/>
<part name="U$1" library="enfolib" deviceset="CONN-4" device=""/>
</parts>
<sheets>
<sheet>
<plain>
<text x="103.886" y="29.21" size="3.81" layer="94">Sigurd M. Albrektsen
NTNU 2016</text>
<text x="192.024" y="11.938" size="2.54" layer="94">1.0</text>
NTNU 2017</text>
<text x="192.024" y="11.938" size="2.54" layer="94">2.0</text>
<frame x1="0" y1="0" x2="208.28" y2="106.68" columns="3" rows="2" layer="94"/>
</plain>
<instances>
......@@ -7251,7 +7303,8 @@ NTNU 2016</text>
<instance part="C3" gate="G$1" x="33.02" y="60.96"/>
<instance part="FRAME1" gate="G$1" x="101.6" y="5.08"/>
<instance part="JST-SM10B-GHDS" gate="G$1" x="129.54" y="66.04"/>
<instance part="R2" gate="G$1" x="27.94" y="88.9" rot="R90"/>
<instance part="J1" gate="G$1" x="27.94" y="88.9" rot="R90"/>
<instance part="U$1" gate="B" x="129.54" y="91.44" rot="R180"/>
</instances>
<busses>
</busses>
......@@ -7277,7 +7330,7 @@ NTNU 2016</text>
<junction x="25.4" y="78.74"/>
<wire x1="33.02" y1="86.36" x2="38.1" y2="86.36" width="0.1524" layer="91"/>
<wire x1="38.1" y1="86.36" x2="38.1" y2="78.74" width="0.1524" layer="91"/>
<pinref part="R2" gate="G$1" pin="1"/>
<pinref part="J1" gate="G$1" pin="1"/>
<wire x1="33.02" y1="86.36" x2="33.02" y2="83.82" width="0.1524" layer="91"/>
<wire x1="33.02" y1="83.82" x2="27.94" y2="83.82" width="0.1524" layer="91"/>
</segment>
......@@ -7321,6 +7374,21 @@ NTNU 2016</text>
<junction x="139.7" y="71.12"/>
<label x="142.24" y="71.12" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U$1" gate="B" pin="MNT"/>
<wire x1="137.16" y1="96.52" x2="139.7" y2="96.52" width="0.1524" layer="91"/>
<label x="139.7" y="96.52" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U$1" gate="B" pin="2"/>
<wire x1="121.92" y1="91.44" x2="116.84" y2="91.44" width="0.1524" layer="91"/>
<label x="116.84" y="91.44" size="1.778" layer="95" rot="R180"/>
</segment>
<segment>
<pinref part="U$1" gate="B" pin="4"/>
<wire x1="121.92" y1="86.36" x2="116.84" y2="86.36" width="0.1524" layer="91"/>
<label x="116.84" y="86.36" size="1.778" layer="95" rot="R180"/>
</segment>
</net>
<net name="VDDRTC" class="0">
<segment>
......@@ -7331,7 +7399,7 @@ NTNU 2016</text>
<label x="48.26" y="88.9" size="1.778" layer="95"/>
<wire x1="45.72" y1="88.9" x2="48.26" y2="88.9" width="0.1524" layer="91"/>
<junction x="45.72" y="88.9"/>
<pinref part="R2" gate="G$1" pin="2"/>
<pinref part="J1" gate="G$1" pin="2"/>
<wire x1="27.94" y1="93.98" x2="33.02" y2="93.98" width="0.1524" layer="91"/>
<wire x1="33.02" y1="93.98" x2="33.02" y2="88.9" width="0.1524" layer="91"/>
</segment>
......@@ -7402,6 +7470,11 @@ NTNU 2016</text>
<wire x1="83.82" y1="58.42" x2="86.36" y2="58.42" width="0.1524" layer="91"/>
<label x="86.36" y="58.42" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U$1" gate="B" pin="3"/>
<wire x1="121.92" y1="88.9" x2="116.84" y2="88.9" width="0.1524" layer="91"/>
<label x="116.84" y="88.9" size="1.778" layer="95" rot="R180"/>
</segment>
</net>
<net name="DIO3" class="0">
<segment>
......@@ -7409,6 +7482,11 @@ NTNU 2016</text>
<wire x1="83.82" y1="60.96" x2="86.36" y2="60.96" width="0.1524" layer="91"/>
<label x="86.36" y="60.96" size="1.778" layer="95"/>
</segment>
<segment>
<pinref part="U$1" gate="B" pin="1"/>
<wire x1="121.92" y1="93.98" x2="116.84" y2="93.98" width="0.1524" layer="91"/>
<label x="116.84" y="93.98" size="1.778" layer="95" rot="R180"/>
</segment>
</net>
<net name="SCLK" class="0">
<segment>
......